Random Access Memory cells or RAM cells have become increasingly popular due in part to the attractive costs of these devices. Many such conventional RAM cells are ordinarily only addressable from a single port. In such a memory apparatus, the input of an address causes a single select line or a coincidence of two select lines, such as a row select line and a column select line, to cause the addressed cell to be selected. Upon selection of a cell, data may then be sensed from or written into the selected storage cell on one or two bit sense lines. Alternatively, in some RAM cells, a single selection line causes the particular cell to be selected, and other selection circuitry activated by the same address causes the bit-sense lines to be selected. However, there are never any options for reading and writing at the same time. The same selection lines and the same bit sense lines are always utilized to access and write or read the content of a particular location. Consequently, a single port RAM memory device cannot be simultaneously addressed and accessed from separate sources.
Certain applications require higher memory access speeds. Examples of such high speed applications may be graphic related memory systems such as those used in a computer display systems, data transfer and buffering devices used in high speed communication systems, and memory systems used in conjunction with arithmetic logic units. For such applications, multiport random access memory devices have been developed to provide increased accessibility to the memory contents of the random access memory unit and more flexibility for inter-processor communications. One example of a multi-port memory device is a dual-port RAM cell accessible simultaneously by two independent entities. In digital integrated circuits (ICs), this implies a dual-port memory cell that can be accessed at the same time through two different ports. Each port utilizes independent sets of addresses and control lines to access the memory array.
FIG. 1 shows a block diagram of an implementation of a conventional dual-ported memory system 100. As shown in FIG. 1, this implementation of a dual ported memory cell supports multiple clock domains. A true dual port memory system provides simultaneous access to any location in the memory, wherein either port can be used to read or write data into and out of any memory location at the same time. Additionally, some dual port memory systems include the ability to run each port on an independent clock domain, enabling the processing of large amounts of data very efficiently and quickly. Independent clock domains also enable communication between multiple processors and solves the rate-mismatch problem caused by processors operating at different speeds.
Although the conventional dual port memory system 100 of FIG. 1 provides for an effective solution for operations requiring high memory access speeds, it may result in a large circuit design and relatively high development costs. For the same density, a dual port memory is approximately twice the size of a single port memory. Additionally, for each new generation of fabrication process technology, a new dual port cell must be designed and tested, leading to additional development expenses.
FIG. 2 shows a block diagram of a second conventional implementation of a dual ported memory device 200. As shown in FIG. 2, a single ported memory 202 is used for data that is communicated across clock boundaries. In this system, data crosses the clock domain boundary 204 through a first in first out (FIFO) memory 206. The data is synchronized to the second clock domain 208 through this FIFO 206. This method of data transfer is used for sequential data processing and is unidirectional. As shown in FIG. 2, the address for the data is generated in the second clock domain and does not cross the clock boundary 204. The memory system 200 is more size efficient than the dual port memory system 100 of FIG. 1. However, the memory system of FIG. 2 is most suitable for unidirectional and sequential data flow only. The dual port memory system 200 is not well adapted to handling bi-directional input and output access to the memory device. Furthermore, whenever a system runs on or is synchronized to more than one clock, a degree of uncertainty is inherent in the system.